WHY CF-1
Physical AI shouldn't cost a data-centre power budget
Machines that sense and act need real-time AI on a battery. General-purpose chips spend power and area on capability those workloads never use. CF-1 is sized to the job — so more of every milliwatt goes into inference.
Low power by design
A 3–5 W target, with an architecture chosen for performance per watt from the first simulation — not tuned for it after the fact.
Built for transformers
Hardware attention, softmax, and layer-norm, with a DRAM interface — so vision-language and multimodal models run on the device, with deterministic latency.
Designed in India
Architecture, IP, and design files developed and held in India — a trusted, domestic source for edge AI silicon.
WHERE IT RUNS
Built for machines that sense and act
HOW IT'S BUILT
Every stage of our platform, applied to one chip
CF-1 is the proof of our own pipeline: the same loop we run for customers, run first on ourselves.
01 · WORKLOAD INTELLIGENCE
Profiled the edge vision and sensor-fusion models CF-1 must run.
02 · VIRTUAL SILICON
Simulated candidate architectures against those workloads before layout.
03 · ARCHITECTURE EXPLORER
Selected the design with the best measured performance per watt.
04 · PRE-SILICON VALIDATION
Proving it on real FPGA hardware before tapeout.
TARGET SPECIFICATIONS
CF-1 at a glance
Design targets for CF-1. Final figures are confirmed at FPGA and silicon validation.
Performance
20–32 TOPS (INT8, dense); about 2× at INT4
Efficiency
5–8 TOPS/W
Power envelope
3–5 W typical; under 8 W peak; passive cooling
Precision
INT4, INT8, FP16; FP8 targeted
Transformer support
Hardware attention, softmax, and layer-norm
Memory
LPDDR4X / LPDDR5 interface, 25–50 GB/s
Camera and sensor inputs
Up to 4× MIPI CSI-2; SPI / I²C for IMU, lidar, and radar
Host interface
PCIe Gen3/Gen4 ×4; M.2 module form factor
Latency
Under 10 ms for detection; deterministic scheduling
Target models
YOLO-class detection, depth and segmentation, BEV fusion, 1–3B-parameter vision-language models
Frameworks
ONNX, PyTorch export, TensorFlow Lite; ROS 2 integration
Process node
28 nm / 22 nm
Operating temperature
–40 to 85 °C (industrial grade)
Availability
[STATUS — e.g. FPGA prototype in development; test chip to follow]
ROADMAP
From FPGA to a family of physical-AI chips
NOW
CF-1 FPGA prototype
Architecture validated on target physical-AI models, with measured numbers.
NEXT
CF-1 test chip
A smaller die on a 28/22 nm multi-project wafer, proving the silicon works.
THEN
CF-1 production
Full specification, packaged and tested, moving onto our Uttar Pradesh line.
LATER
CF-2
12/16 nm, 100+ TOPS, for humanoids and vision-language-action models.
Building a machine that senses and acts?
We're working with a small group of robotics and physical-AI design partners to shape CF-1 around real workloads. Tell us what your machine needs to run.
Become a design partner